If you've been hesitant to add IEEE 1149.7 capabilities to your next chip because you believe it means abandoning your previous investment and experience in IEEE 1149.1, you're not alone. The notion that IEEE 1149.7 replaces IEEE 1149.1 is a myth (or, more to the point, a bit of misinformation) that has managed to spread itself around. The true story has a much happier ending.
IEEE 1149.7 (also known as compact JTAG or cJTAG) offers several benefits over traditional IEEE 1149.1 (JTAG), but it does not require you to change your existing on-chip JTAG infrastructure. On the contrary; IEEE 1149.7 simply provides new and better ways to take advantage of your existing IEEE 1149.1 on-chip test logic.
All you have to do is insert the cJTAG-IEEE 1149.7 IP from IPextreme between your existing IEEE 1149.1 TAP Controller and your chip's JTAG I/O pins and your chip is cJTAG-enabled.
And what does that mean?
Well, for one thing, your on-chip JTAG functions (IEEE 1149.1 boundary scan and/or application-specific test/debug strategies) will work as they did before; the presence of the cJTAG IP is transparent to your on-chip IEEE 1149.1 TAP Controller. So, there is no need to re-design your on-chip test logic. And, when operating in an IEEE 1149.1 series scan environment, the cJTAG IP is transparent to both the tester and the on-chip test logic.
Beyond that, usage of the added IEEE 1149.7 capabilities depends on the external environment: the capabilities test/debug hardware and software, the capabilities of other devices on the scan chain, and how the devices are connected together. Here are a few examples of the capabilities that you gain with a cJTAG-enabled chip:
So what's the point?
Taking advantage of IEEE 1149.7 features such as star topologies and 2-pin operation involves two distinct activities:
(a) Adding IEEE 1149.7 capabilities to your chip
(b) Developing a system-level test/debug solution that uses those capabilities
With the cJTAG IP from IPextreme, activity (a) is really just a simple integration task. For a few on-chip signal connections and about 2500 gates, your IEEE 1149.1 enabled chip becomes IEEE 1149.7 enabled. There is no need to re-work your existing IEEE 1149.1 on-chip test logic. And the chip will continue to work as before in an IEEE 1149.1 test environment.
Activity (b) is a system-level test/debug task for which you will need an IEEE 1149.7 capable test platform and, for example, to create star topologies, other IEEE 1149.7 capable devices. With the CJTAG IP integrated into the chip, you will be able to take advantage of the growing availability of IEEE 1149.7 capable devices and test/debug platforms.
IEEE 1149.7 (also known as compact JTAG or cJTAG) offers several benefits over traditional IEEE 1149.1 (JTAG), but it does not require you to change your existing on-chip JTAG infrastructure. On the contrary; IEEE 1149.7 simply provides new and better ways to take advantage of your existing IEEE 1149.1 on-chip test logic.
All you have to do is insert the cJTAG-IEEE 1149.7 IP from IPextreme between your existing IEEE 1149.1 TAP Controller and your chip's JTAG I/O pins and your chip is cJTAG-enabled.
And what does that mean?
Well, for one thing, your on-chip JTAG functions (IEEE 1149.1 boundary scan and/or application-specific test/debug strategies) will work as they did before; the presence of the cJTAG IP is transparent to your on-chip IEEE 1149.1 TAP Controller. So, there is no need to re-design your on-chip test logic. And, when operating in an IEEE 1149.1 series scan environment, the cJTAG IP is transparent to both the tester and the on-chip test logic.
Beyond that, usage of the added IEEE 1149.7 capabilities depends on the external environment: the capabilities test/debug hardware and software, the capabilities of other devices on the scan chain, and how the devices are connected together. Here are a few examples of the capabilities that you gain with a cJTAG-enabled chip:
- The ability to operate in a star topology: Chips connected in parallel means a shorter path to the chip of interest. And that means faster scan operations. Device selection occurs between the cJTAG IP and the tester. Your on-chip IEEE 1149.1 TAP Controller sees only a direct connection to the tester.
- Shorter series scan paths: In a series topology, you can reduce the length of your series scan path by using the IEEE 1149.7 Super-Bypass feature. With Super-Bypass activated, the cJTAG IP provides 1-bit IR and DR scan paths, bypassing your IEEE 1149.1 TAP Controller. Again, there is no need to change to your existing on-chip IEEE 1149.1 test infrastructure - it is simply bypassed when it is not the target of a series scan operation.
- The option to use fewer chip-level test pins: The cJTAG IP can use either a 4-pin or 2-pin interface to the tester. When operating in 2-pin mode, the cJTAG IP continues to present the traditional 4-pin (TCK, TMS, TDI, TDO) JTAG interface to the on-chip TAP Controller while communicating with the tester using only TCK and TMS (or, more correctly, TCKC and TMSC in the IEEE 1149.7 2-pin nomenclature). If your device uses nTRST, there's more good news. The cJTAG IP can accept IEEE 1149.7 reset signalling through the 2-pin interface and send your on-chip IEEE 1149.1 TAP Controller a good old-fashioned nTRST pulse; so you no longer need a chip-level nTRST pin.
So what's the point?
Taking advantage of IEEE 1149.7 features such as star topologies and 2-pin operation involves two distinct activities:
(a) Adding IEEE 1149.7 capabilities to your chip
(b) Developing a system-level test/debug solution that uses those capabilities
With the cJTAG IP from IPextreme, activity (a) is really just a simple integration task. For a few on-chip signal connections and about 2500 gates, your IEEE 1149.1 enabled chip becomes IEEE 1149.7 enabled. There is no need to re-work your existing IEEE 1149.1 on-chip test logic. And the chip will continue to work as before in an IEEE 1149.1 test environment.
Activity (b) is a system-level test/debug task for which you will need an IEEE 1149.7 capable test platform and, for example, to create star topologies, other IEEE 1149.7 capable devices. With the CJTAG IP integrated into the chip, you will be able to take advantage of the growing availability of IEEE 1149.7 capable devices and test/debug platforms.
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