It goes without saying that the semiconductor industry today is fueled by third-party IP. This is plainly illustrated by a recent graph from Semico Research Corporation showing the explosive application of IP reuse over the last 15 years. Today’s SoC averages over 150 reused blocks comprising 60 to 70% of the die area.
A recent press release from the EDA Consortium shows that in Q3 2015, semiconductor IP revenue exceeded EDA revenue for the first time. The design efficiency enabled by IP reuse is here to stay, and there is no turning back the clock.
But for all its benefits, does IP reuse also have a downside?
John Locke, a noted 17th Century English philosopher, was first to talk about “unintended consequences” in the social context, explaining that seemingly positive actions may sometimes give rise to negative consequences. The benefits of IP reuse fall into much the same category. IP reuse has enabled gigantic leaps in productivity and cost efficiency, but it has brought with it the hidden consequence of unseen, unknown liabilities that lay coiled like a snake under the table, waiting to strike.
The dirty little secret of today’s semiconductor industry is this: most companies have—at best—ad-hoc methods for keeping track of the massive amount of IP that is coming through their doors from an ever-growing number of suppliers. “Keeping track” is actually much more difficult than the casual observer might think, as not only the actual IP data (RTL, GDSII, documentation, etc.) itself needs to be tracked; equally important is the veritable mountain of metadata that is associated with the licensing conditions applicable to the IP.
A common refrain in talking to many IP administrators is that there is a problem, but it has not yet reached crisis level within these companies. Effectively, this means that until it becomes a real problem, no one is going to fix it. People are simply overloaded with no budget or time allocated for them to focus on IP management. In the words of an anonymous IP manager from a Top 10 semiconductor company:
The fact of the matter is that we are almost certainly using IP without the proper license in place. The problem is we don’t know which IP or exactly how we are misusing it. We are forced to do the best we can, with the resources we have.
The root cause for such statements, according to Eric Stein, Director of Forensics, PricewaterhouseCoopers, is what he calls “unintended reuse,” which occurs when an engineer uses an IP without actually knowing that he/she is violating the contract terms. Common scenarios for such a violation are as follows:
- A chip design database, including all the 3rd-party IP therein, is copied from one project to the next. The engineering team may be different and unaware of what is internal IP and what is 3rd-party IP.
- Contract terms are not visible to engineers. Engineers may erroneously believe that since the IP was used in a past project, the company “bought it.” Many are not familiar with the concept of per-use licensing.
- All projects are not visible to IP procurement managers, especially in a large global organization. They have no way to check that the IP has the proper license, in part because they may not even know that someone in another region is using it.
While these types of problems are clearly unintentional, it doesn’t diminish the liability that a company can face if the IP supplier suspects a compliance issue or if an auditor discovers such an issue. Aside from recovering license fees, a company may face penalties or even seek an injunction until the issue is satisfactorily resolved. In such cases, the IP supplier is in a position of extreme power. With the amount of IP reuse increasing year over year, the amount of unknown liability only increases.
The root cause of this problem is that, unlike EDA tools, IP is mostly a source code business, and source code is easy to share but hard to track. Once it is “released into the wild” on a company’s file servers, it can be difficult to locate all of its copies.
There have been efforts over the last 15 years to develop tracking standards, one of those being “tags” that are written onto a GDSII layer as textual information regarding IP contained in the chip. The first of these was the Hard IP Tagging Standard that was released in 2004. This worked well for hard IP, but didn’t address the topic of soft (digital) IP. In 2013, Accelera released an update to the standard to support Soft IP Tagging. This soft IP tagging standard described the mechanism for how tags would be represented in the GDSII, but left the implementation to the industry. In the ensuing years, no solution has emerged because it requires fundamental changes the EDA design flow to propagate EDA information from RTL to GDSII. This is a tall order, however, as it necessitates that all the major EDA companies agree on a standard IP-aware design flow. The veterans of this industry are surely aware that this is a slow process, if not an impossible one.
The good news is that through a new initiative called the Core Store, IPextreme has introduced a new, groundbreaking technology called “IP Fingerprinting” that greatly solves the issue of unintended IP reuse. It offers enormous benefits to both IP providers and their customers.
The fingerprinting use model is extremely simple:
- IPs are fingerprinted and those fingerprints stored in a central place
- The SoC is also fingerprinted
- A “Chip DNA Analysis” tool searches the SoC fingerprint for matches from within the repository of IP fingerprints
- A report is issued that indicates:
- What IP was detected
- What IP was partially detected
- The version of the IP that was detected
- Any files of that IP that were modified
- Any GDSII tags that were detected
Like the fingerprinting use model itself, a fingerprint is an extremely simple concept, using a technique to create a unique digital representation of an IP block or SoC. In a nutshell, a fingerprint is:
- A secure, compact digital summary of all the files contained in an IP/SoC
- Extremely small: only 75B for each file contained in the IP/SoC
- A plain text file (standard JSON format) to allow all parties to see the fingerprint data
- Impossible to reverse engineer, for maximum security
One of the key advantages to fingerprinting is that it requires no extra information to be added to either the IP or SoC to facilitate tracking and requires no change to the EDA flow. Furthermore, it can be applied not only to semiconductor IP, but also to embedded software that may also have licensing implications.
Fingerprinting is accomplished through the use of a free fingerprinting app available from the Core Store for IP companies and semiconductor companies. Semiconductor companies have access to the Chip DNA Analysis software on either a standalone subscription model or included for free if they own a Xena® Enterprise server, which can be used to manage fingerprints, IP data, and IP metadata in a completely integrated environment.
A white paper with more technical details on IP Fingerprinting is available on the Core Store.
With the advance of new technologies and methodologies like Xena and IP Fingerprinting, we are on the way to taking the industry to new levels of efficiency without the liabilities. Fingerprinting makes the unintended consequences of IP reuse a thing of the past.